In a conventional shared-memory multi-core processor system, each central processing unit (CPU) of the multi-core processor has therein high-speed small-capacity distributed cache memory. A hierarchical cache is known that is formed by disposing intermediate-speed intermediate-capacity shared caches in one or more hierarchies between the distributed cache and the shared memory. It is assumed that the distributed cache is closest to the CPU and that the closer a cache is to the CPU, the higher the cache is in the hierarchy.
The hierarchical cache is designed such that an intermediate-hierarchy cache has a lower access speed than that of a higher-hierarchy cache and has a larger capacity than that of the higher-hierarchy cache, and has a higher access speed than that of an lower-hierarchy cache and has a smaller capacity than that of the lower-hierarchy cache.
In the hierarchical cache, when data to be read is not stored in a higher-hierarchy cache, the data is read from a lower-hierarchy cache and is simultaneously stored in the higher-hierarchy cache. When the data to be read is also not stored in the lower-hierarchy cache, the reading is tried of the data from a cache in a further lower hierarchy. It is known that, when the data to be read is not stored even in the lowest-hierarchy cache, an operation is executed to read the data from the shared memory.
In the case where data is newly stored in a cache, when the cache memories are already full, the data to be removed is determined by a cache controller employing a least recently used (LRU) scheme, etc. The data determined to be removed is written back into the shared memory for a single-hierarchy cache. However, the removed data is stored in a cache whose hierarchy is lower by one hierarchy, in a multi-hierarchy cache. The new data is stored in an area that is cleared by the removal operation. Thereby, in the multi-hierarchy cache, even when the capacity of a higher-hierarchy cache is full, while the removed data remains in a lower-hierarchy cache, the data is accessible at a higher speed than that for the shared memory.
A technique is known according to which a CPU directly accesses shared memory to increase the speed of reading data when traffic is high consequent to access of a cache memory (see, e.g., Japanese Laid-Open Patent Publication No. 2008-117388).
When the shared cache is present in a hierarchy that is lower than the distributed cache, the shared cache is designed to have a capacity that is larger than the total capacity of the distributed caches in hierarchies that are higher than the shared cache such that the data overflowing from each of the distributed caches can be stored. Plural CPUs simultaneously execute processing in the multi-core processor system and therefore, data overflowing and removed from each of the distributed caches enters the shared cache and competition to acquire the shared cache occurs. For example, when one CPU executes a process using a large amount of data, a lower shared cache memory is filled with the data overflowing from the distributed cache memory of the CPU. Therefore, any other CPU can substantially not use the lower shared cache memory.
When a large-sized apparatus or a general-purpose apparatus has a large shared cache memory, the shared cache memory can store therein a large amount of data. However, an embedded multi-core processor system provided in a portable apparatus has a shared cache memory that is about several to several ten times as small as that of a large-sized apparatus or the general purpose apparatus. Therefore, in the embedded multi-core processor, even for an ordinary process using a small amount of data, plural CPUs simultaneously execute a thread. Therefore, a problem arises in that competition occurs to acquire the area of the shared cache memory.